`timescale 1ns / 1ps
//********************************************************************** 
// -------------------------------------------------------------------
// Disclaimers
// -------------------------------------------------------------------
// When you use this source file, please note that the author assumes 
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// If you do not agree to the terms, please do not use the file and 
// delete the file promptly.
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// Copyright Notice
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// This source file may be used for personal study, provided that this 
// copyright notice is not removed from the file.
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// ------------------------------------------------------------------- 
// Author: Geeker_FPGA 
// Email:geeker_fpga@uisrc.com
// Date:2022/04
// Description: 
//  
// 
// Web:http://www.uisrc.com
//------------------------------------------------------------------- 
//*********************************************************************/
module udp_fifo#(
	parameter FIFO_PTR     = 4,     
	parameter FIFO_WIDTH   = 8,
	parameter FIFO_MODE    = "NORMAL"//"NORMAL" "SHOWAHEAD"
)(
    rst           ,
    wr_clk        ,
    rd_clk        ,
    din           ,
    wr_en         ,
    rd_en         ,
    dout          ,
    full          ,
    empty         ,
    rd_data_count ,
    wr_data_count 
);

input wire 						rst          ;
input wire 						wr_clk       ;
input wire 						rd_clk       ;
input wire 	[FIFO_WIDTH-1:0]	din          ;
input wire 						wr_en        ;
input wire 						rd_en        ;
output wire [FIFO_WIDTH-1:0]	dout         ;
output wire 					full         ;
output wire 					empty        ;
output wire [FIFO_PTR:0]		rd_data_count;
output wire [FIFO_PTR:0]		wr_data_count;

asynch_fifo#(
	.FIFO_PTR   		( FIFO_PTR		),     
	.FIFO_WIDTH 		( FIFO_WIDTH	),
	.FIFO_MODE 			( "SHOWAHEAD"   )//"NORMAL" "SHOWAHEAD" 
)u_asynch_fifo
(
	.fifo_wrclk     	(wr_clk			),
	.fifo_wr_rst_n  	(!rst			),
	.fifo_wren      	(wr_en			),
	.fifo_wrdata    	(din			),
	.fifo_rdclk     	(rd_clk			),
	.fifo_rd_rst_n  	(!rst			),
	.fifo_rden      	(rd_en			),
	.fifo_rddata    	(dout			),
	.fifo_full      	(full			),
	.fifo_empty     	(empty			),
	.fifo_afull     	(				),
	.fifo_aempty    	(				),
	.fifo_room_avail  	(wr_data_count	),
	.fifo_data_avail  	(rd_data_count	)
);

endmodule